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june 2007 rev 3 1/22 1 l6727 single phase pwm controller feature flexible power supply from 5v to 12v power conversion input as low as 1.5v 1% output voltage accuracy high-current integrated drivers adjustable output voltage 0.8v internal reference simple voltage mode control loop sensorless and programmable ocp across low-side r dson oscillator internally fixed at 300khz internal soft-start ls-less to manage pr e-bias start-up disable function ov / uv protection fb disconnection protection so-8 package applications subsystem power supply (mch, ioch, pci...) memory and termination supply cpu & dsp power supply distributed power supply general dc / dc converters description l6727 is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protections and reference voltage to realize in an easy and simple way general dc-dc converters by using a compact so-8 package. device flexibility allows managing conversions with power input v in as low as 1.5v and device supply voltage in the range of 5v to 12v. l6727 provides simple control loop with voltage- mode error-amplifier. the integrated 0.8v reference allows regulating output voltages with 1% accuracy over line and temperature variations. oscillator is internally fixed to 300khz. l6727 provides programmable over current protection as well as over and under voltage protection. current information is monitored across the low-side mosfet r dson saving the use of expensive and space-consuming sense resistors while output voltage is monitored through fb pin. fb disconnection protection prevents excessive and dangerous output voltages in case of floating fb pin. so-8 table 1. device summary part number package packaging l6727 so-8 tube L6727TR so-8 tape & reel www.st.com
contents l6727 2/22 contents 1 typical application cir cuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 soft start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 low-side-less start up (lsless) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 over current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 output voltage monitor and pr otections . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 under voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.3 feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.4 under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
l6727 contents 3/22 9 application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.2 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.3 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.4 embedding l6727-based vrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
typical application circuit and block diagram l6727 4/22 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical application circuit 1.2 block diagram figure 2. block diagram hs ls v in = 1.5v to 19v (**) l c out vout load c hf c bulk r d c sn r sn c boot r ghs r gls d 1 2 8 boot ugate phase lgate 4 c dec fb 6 r fb comp / dis / oc 7 r f c f c p gnd vcc r os v cc = 5v to 12v r ocset (*) 5 3 l6727 reference schematic (*) r ocset not to be connected when vcc > 5v l6727 (**) up to 12v with vcc > 5v vcc boot lgate fb ugate comp / dis / oc gnd adaptive anti cross conduction hs ls vcc error amplifier + - 0.8v 300 khz oscillator pwm phase control logic & protections current read & ocp disable vout monitor i ocset l6727
l6727 pins description and connection diagrams 5/22 2 pins description and connection diagrams figure 3. pins connection (top view) 2.1 pin descriptions table 2. pins descriptions 1 2 3 4 vcc fb comp / dis / oc phase lgate gnd ugate boot 5 6 7 8 l6727 pin # name function 1boot hs driver supply. connect through a capacitor (100nf) to the floating node (ls-drain) pin and provide necessary bootstrap diode from vcc. 2 ugate hs driver output. connect to hs mosfet gate. 3gnd all internal references, logic and drivers are connected to this pin. connect to the pcb ground plane. 4 lgate ls driver output. connect to ls mosfet gate. 5vcc device and ls driver power supply. operative range from 4.1v to 13.2v. filter with at least 1 f mlcc to gnd. 6fb error amplifier inverting input. connect with a resistor r fb to the output regulated voltage. additional resistor r os to gnd may be used to regulate voltages higher than the reference. 7 comp / dis / oc comp . error amplifier output. connect with an r f - c f // c p to fb to compensate the control-loop. dis . the device can be disabled by forcing this pin lower than 0.5v(typ). to disable the device, the external pull-down need to overcome 10ma of comp output current for about 15 s. once disabled, comp output current drops to 20 a. oc. over current threshold set. connect with an r ocset resistor to vcc (only if vcc is supplied by 5v bus) to program oc threshold. when vcc > 5v, r ocset need to be not-connected. 8 phase hs driver return path, current-reading and adaptive-dead-time monitor. connect to the ls drain to sense r dson drop to measure the output current. this pin is also used by the adaptive-dead-time control circuitry to monitor when hs mosfet is off.
electrical specifications l6727 6/22 2.2 thermal data table 3. thermal data 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings symbol parameter value unit r thja thermal resistance junction to ambient (1) 1. measured with the component mounted on a 2s2p board in free air (6.7cm x 6.7cm, 35 m (p) and 17.5 m (s) copper thickness). 85 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range -20 to 150 c symbol parameter (1) 1. esd immunity for fb pin is guarant eed up to 1000v (human body model). value unit v cc to gnd -0.3 to 15 v v boot to phase to gnd 15 45 v v ugate to phase to phase; t < 50ns to gnd -0.3 to (v boot - v phase ) + 0.3 -1 v boot + 0.3 v v phase to gnd -8 to 30 v v lgate to gnd to gnd; t < 50ns -0.3 to v cc + 0.3 -1 v comp to gnd -0.3 to 7 v fb to gnd -0.3 to 3.6 v
l6727 electrical specifications 7/22 3.2 electrical characteristics table 5. electrical characteristics (v cc = 12v; t a = -20 c to +85 c, unless otherwise specified). symbol parameter test conditions min. typ. max. unit recommended operating conditions v cc device supply voltage see figure 1 4.1 13.2 v v in conversion input voltage 13.2 v v cc < 7.0v 19.0 v supply current and power-on i cc vcc supply current ugate and lgate = open 6 ma i boot boot supply current ugate = open; phase to gnd 0.5 ma uvlo vcc turn-on vcc rising 4.1 v hysteresis 0.2 v oscillator f sw main oscillator accuracy 0 c to +70 c 270 300 330 khz 250 300 350 khz ? v osc pwm ramp amplitude 1.5 v d max maximum duty cycle 80 % reference output voltage accuracy v out = 0.8v, t a = 0c to 70c -1 - 1 % v out = 0.8v -1.5 1.5 % error amplifier a 0 dc gain (1) 120 db gbwp gain-bandwidth product (1) 15 mhz sr slew-rate (1) 8v/ s i fb input bias current sourced from fb 100 na dis disable threshold comp falling 0.43 0.5 v
electrical specifications l6727 8/22 gate drivers i ugate hs source current boot - phase = 5v to 12v 1.5 a r ugate hs sink resistance boot - phase = 5v to 12v 1.1 ? i lgate ls source current vcc = 5v to 12v 1.5 a r lgate ls sink resistance vcc = 5v to 12v 0.65 ? over-current protection i ocset ocset current source sunk from comp pin, before ss 55 60 65 a v cc_oc oc switch-over threshold vcc rising 8 v v octh fixed oc threshold v phase to gnd, vcc > v cc_oc -400 mv over & under-voltage protections ovp ovp threshold fb rising 1 v uvp uvp threshold fb falling 0.6 v 1. guaranteed by design, not subject to test. table 5. electrical characteristics (continued) (v cc = 12v; t a = -20 c to +85 c, unless otherwise specified). symbol parameter test conditions min. typ. max. unit
l6727 device description 9/22 4 device description l6727 is a single-phase pwm controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general dc- dc step-down converter. designed to drive n-channel mosfets in a synchronous buck topology, with its high level of in tegration this 8-pin device allows reducing cost and size of the power supply solution. l6727 is designed to operate from a 5v or 12v supply bus. thanks to the high precision 0.8v internal reference, the output voltage can be precisely regulated to as low as 0.8v with 1% accuracy over line and temperature variations (between 0c and +70c). the switching frequency is internally set to 300khz. this device provides a simple control loop with a voltage-mode error-amplifier. the error- amplifier features a 15mhz gain-bandwidth product and 8v/s slew rate, allowing high regulator bandwidth for fast transient response. to avoid load damages, l6727 provides over current protection as well as over voltage, under voltage and feedback disconnection protection. when the device is supplied from 5v, over current trip threshold is programmable by a simple resistor. output current is monitored across low-side mosfet r dson , saving the use of expensive and space-consuming sense resistor. output voltage and feedback disconnection are monitored through fb pin. l6727 implements soft-start increasing the internal reference from 0v to 0.8v in 5.1ms (typ) in closed loop regulation. low-side-less feature allows the device to perform soft-start over pre-biased output avoiding high current return through the output inductor and dangerous negative spike at the load side.
driver section l6727 10/22 5 driver section the integrated high-current drivers allow using different types of power mosfet (also multiple mosfets to reduce the equivalent r dson ), maintaining fast switching transition. the driver for the high-side mosfet uses bo ot pin for supply and phase pin for return. the driver for low-side mosfet uses the vcc pin for supply and gnd pin for return. the controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of schottky diode: to check high-side mosfet turn off, ph ase pin is sensed. when the voltage at phase pin drops down, the low-side mosfet gate drive is suddenly applied; to check low-side mosfet turn off, lgate pin is sensed. when the voltage at lgate has fallen, the high-side mosfet gate drive is suddenly applied. if the current flowing in the in ductor is negative, voltage on phase pin will never drop. to allow the low-side mosfet to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side mosfet doesn't drop, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. power conversion input is flexible: 5v, 12v bus or any bus that allows the conversion (see maximum duty cycle limitation and recommended operating conditions, in ta b l e 5 ) can be chosen freely. 5.1 power dissipation l6727 embeds high current mosfet drivers for both high side and low side mosfets: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. two main terms contribute in the device power dissipation: bias power and drivers' power. device bias power (p dc ) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply hs and ls drivers with the same vcc of the device): drivers power is the power needed by the driver to continuously switch on and off the external mosfets; it is a function of the switching frequency and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw dissipated to switch the mosfets (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet resistance and intrinsic driver resistance. this last term is the important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfets results: where v boot - v phase is the voltage across the bootstrap capacitor. external gate resistors helps the device to dissipate the switching power since the same power p sw will be shared between the internal driv er impedance and the external resistor resulting in a general cooling of the device. p dc v cc i cc i boot + () ? = p sw f sw q ghs v boot v phase ? () q gls v cc ? + ? [] ? =
l6727 soft start and disable 11/22 6 soft start and disable l6727 implements a soft start to smoothly charge the output filter avoiding high in-rush currents to be required from the input power supply. the device progressively increases the internal reference from 0v to 0.8v in about 5.1ms, in closed loop regulation, gradually charging the output capacitors to the final regulation voltage. in the event of an over current triggering during soft start, the over current logic will override the soft start sequence and will shut down both the high side and low side gates for the internal soft start residual time (up to 2048 cl ock cycles) plus 2048 clock cycles, then it will begin a new soft start. the device begins soft start phase only when vcc power supply is above uvlo threshold and over current threshold setting phase has been completed. 6.1 low-side-less start up (lsless) in order to manage start up over pre-biased output, l6727 performs a special sequence in enabling ls driver to switch: during the soft-start phase, ls driver results disabled (ls = off) until hs starts to switch. this avoids the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. if the output voltage is pre-biased to a voltage lower than the programmed one, neither hs nor ls will turn on until the soft start ramp exceeds the output pre- bias voltage; then v out will ramp up from there, without any drop or current return. if the output voltage is pre-biased to a voltage higher than the programmed one, hs would never start to switch. in this case, at the end of soft start time, ls is enabled and discharges the output to the final regulation value. this particular feature of the device masks the ls turn-on only from the control loop point of view: protections by-pass lsless, turning on the ls mosfet in case of need. figure 4. lsless startup (left) vs. non-lsless startup (right)
soft start and disable l6727 12/22 6.2 enable / disable the device can be disabled by externally pushing comp / dis pin under 0.5v (typ). in disable condition hs and ls mosfets are turned off, and a 20 a current is sourced from comp / dis pin. setting free the pin, this current pulls it over the threshold and the device enables again performing a new ss. to disable the device, the external pull-down needs to overcome 10ma of comp output current for about 15 s. once disabled, comp output current drops to 20 a. figure 5. start up sequence; v cc = 5v (left). over current hiccup (right)
l6727 over current protection 13/22 7 over current protection the over current feature protects the converter from a shorted output or overload, by sensing the output current information across the low side mosfet drain-source on- resistance, r dson . this method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. the low side r dson current sense is impl emented by comparing t he voltage at the phase node when ls mosfet is turned on with the programmed ocp threshold voltage, internally held. if the monitored voltage drop (gnd to phase) exceeds this threshold, an over current event is detected. if two over current events are detected in two consecutive switching cycles, the protection will be triggered and the device will turn off both ls and hs mosfets for 2048 clock cycles (plus internal ss remaining time, if triggered during a ss phase); then it will begin a new soft start. if the over current condition is not removed, the continuous fault will cause l6727 to go into a hiccup mode with a typical period of 13.6ms ( figure 5 ), guaranteeing safe load protection and very low power dissipation. 7.1 over current threshold setting when supplied with vcc = 5v, l6727 allows to easily program an over current threshold ranging from 50mv to 500mv, simply by adding a resistor (r ocset ) between comp and vcc. during a short period of time (5.5ms - 6.5ms) following the first enable (given vcc over uvlo threshold), an internal 60a current (i ocset ) is sunk from comp pin, determining a voltage drop across r ocset . this voltage drop, differentially sensed between vcc and comp, divided by a factor 3, will be sampled an d internally held by the device as over current threshold until next vc c cycling. differential sensin g versus vcc allows ocset procedure to be fully independent from vin rail. the oc setting procedure overall time length ranges from 5.5ms to 6.5ms, proportionally to the threshold being set. connecting an r ocset resistor between comp and vc c, the programme d threshold will be: r ocset values range from 2.5k ? to 25k ? . if the voltage drop across r ocset is too low, the system will be very sensitive to start-up inrush current and noise. this can result in a continuous ocp triggering and hiccup mode. in this case, consider to increase r ocset value. in case r ocset is not connected (and vcc = 5v), the device will set the maximum threshold. if the device is supplied with a vcc higher than 7v, r ocset must be not connected. in this case, as soon as vcc rises over v cc_oc (8v typ.), l6727 switches oc threshold to 400mv (internally fixed value). see figure 5 for oc threshold setting and soft start oscilloscope sample waveforms. i octh 1 3 -- - i ocset r ocset ? r dson ----------------- -------------- ------------ - ? =
output voltage monitor and protections l6727 14/22 8 output voltage monitor and protections l6727 monitors the voltage at fb pin and compares it to internal reference voltage in order to provide under voltage and over voltage protections. 8.1 under voltage protection if the voltage at fb pin drops below uv threshold (0.6v typ), the device turns off both hs and ls mosfets, waits for 2048 clock cycles and then performs a new soft start. if under voltage condition is not removed, the device enters a hiccup mode with a typical period of 13.6ms. uvp is active from the end of soft start. 8.2 over voltage protection if the voltage at fb pin rises over ov threshold (1v typ), over voltage protection turns off hs mosfet and turns on ls mosfet overriding pwm logic as long as over voltage is detected. ovp is always active with top priority as soon as over current threshold setting phase has been completed. 8.3 feedback discon nection protection in order to provide load protection even if fb pin is not connected, a 100na bias current is always sourced from this pin. if fb pin is not connected, this current will permanently pull up fb over ovp threshold: thus ls will be latched on preventing output vo ltage from rising out of control. 8.4 under voltage lock out in order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, uvlo is provided: the device will start up when vcc reaches uvlo upper threshold and will shutdown when vcc drops below uvlo lower threshold. the 4.1v maximum uvlo upper threshold allows l6727 to be supplied from 5v and 12v busses in or-ing diode configuration.
l6727 application details 15/22 9 application details 9.1 output voltage selection l6727 is capable to precisely regulate an output voltage as low as 0.8v. in fact, the device comes with a fixed 0.8v internal reference that guarantees the output regulated voltage to be within 1% tolerance over line and temperature variations between 0c and +70c (excluding output resistor divider tolerance, when present). output voltage higher than 0.8v can be easily achieved by adding a resistor r os between fb pin and ground. referring to figure 1 , the steady state dc output voltage will be: where v ref is 0.8v. 9.2 compensation network the control loop showed in figure 6 is a voltage mode control lo op. the error amplifier is a voltage mode type. the output voltage is regulated to the internal reference (when present, offset resistor between fb node and gnd can be neglected in control loop calculation). error amplifier output is compar ed to oscillator saw-tooth wave form to provide pwm signal to the driver section. pwm signal is then transferred to the switching node with v in amplitude. this waveform is f iltered by the output filter. the converter transfer function is the small signal transfer function between the output of the ea and v out . this function has a double pole at frequency f lc depending on the l-c out resonance and a zero at f esr depending on the output capacitor esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to- peak oscilla tor voltage ? v osc . the compensation network closes the loop joining v out and ea output with transfer function ideally equal to -z f / z fb . figure 6. pwm control loop v out v ref 1 r fb r os ---------- - + ?? ?? ? = l r c out esr r f c f c p r fb c s osc v in ? v osc + + _ _ v out v ref z f z fb pwm comparator error amplifier r s
application details l6727 16/22 compensation goal is to close the control loop assuring high dc regulation accuracy, good dynamic performances and stability. to achiev e this, the overall loop needs high dc gain, high bandwidth and good phase margin. high dc gain is achieved giving an integrator shape to compensation network transfer function. loop bandwidth (f 0db ) can be fixed choosing the right r f /r fb ratio, however, for stability, it should not exceed f sw /2 . to achieve a good phase margin, the control loop gain has to cross 0db axis with -20db/decade slope. as an example, figure 7 shows an asymptotic bode plot of a type iii compensation. figure 7. example of type iii compensation. open loop converter singularities: a) b) compensation network singularities frequencies: a) b) c) d) gain [db] log (freq) 0db open loop ea gain closed loop gain compensation gain open loop converter gain f lc f esr f z1 f z2 f p1 f p2 20log (r f /r fb ) 20log (v in / ? v osc ) f 0db f lc 1 2 lc out ? ---------------------------------- = f esr 1 2 c out esr ?? ------------------------------------------- - = f z1 1 2 r f c f ?? ------------------------------ = f z2 1 2 r fb r s + () c s ?? ----------------------------------------------------- = f p1 1 2 r f c f c p ? c f c p + -------------------- - ?? ?? ?? -------------------------------------------------- = f p2 1 2 r s c s ?? ------------------------------ - =
l6727 application details 17/22 to place the poles and zeroes of the compensation network, the following suggestions may be followed: a) set the gain r f /r fb in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for r fb range from 2k ? to 5k ? ): b) place f z1 below f lc (typically 0.5*f lc ): c) place f p1 at f esr : d) place f z2 at f lc and f p2 at half of the switching frequency: e) check that compensation network gain is lower than open loop ea gain; f) estimate phase margin obtained (it should be greater than 45) and repeat, modifying parameters, if necessary. 9.3 layout guidelines l6727 provides control functions and high current integrated drivers to implement high- current step-down dc-dc converters. in this kind of application, a good layout is very important. the first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage spikes (emi and losses) power connections (highlighted in figure 8 ) must be part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. the critical components, i.e. the power mosfets, must be close one to the other. the use of multi-layer printed circuit board is recommended. the input capacitance (c in ), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. low esr and esl capacitors are preferred, mlcc are suggested to be connected near the hs drain. use proper vias number when power traces have to move between different planes on the pcb in order to reduce both parasitic resistance and inductance. moreover, reproducing the r f r fb ---------- f 0db f lc ------------ ? v osc v in ------------------ - ? = c f 1 r f f lc ?? ----------------------------- = c p c f 2 r f c f f esr 1 ? ??? ---------------------------------------------------------- = r s r fb f sw 2f ? lc ----------------- - 1 ? --------------------------- = c s 1 r s f sw ?? ------------------------------- =
application details l6727 18/22 same high-current trac e on more than one pcb layer will reduce the parasitic resistance associated to that connection. connect output bulk capacitors (c out ) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank. figure 8. power connections (heavy lines) gate traces and phase trace must be sized according to the driver rms current delivered to the power mosfet. the device robustness allows managing applications with the power section far from the controller without losing performances. anyway, when possible, it is recommended to minimize the distance between controller and power section. see figure 9 for drivers current paths. small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. locate bypass capacitor (vcc and bootstrap capacitor) and loop compensation components as close to the device as practical. for over curren t programmability, place r ocset close to the device and avoid leakage current paths on comp / oc pin, si nce the internal current source is only 60 a. systems that do not use schottky diode in parallel to the low-side mosfet might show big negative spikes on the phase pin. this spik e must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to hs mosfet gate, or a phase resistor in series to phase pin), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. this extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings also causing device failures. it is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the bootstrap diode (r d in figure 1 ). figure 9. drivers turn-on and turn-off paths l c in v in ugate phase lgate gnd load l6727 c out r gate r int c gd c gs c ds vcc ls driver ls mosfet gnd lgate r gate r int c gd c gs c ds boot hs driver hs mosfet phase ugate r phase
l6727 application details 19/22 9.4 embedding l6727-based vrs when embedding the vr into the application, additional care must be taken since the whole vr is a switching dc/dc regulator and the most common system in which it has to work is a digital system such as mb or similar. in fact, latest mbs have become faster and more powerful: high speed data busses are more and more common and switching-induced noise produced by the vr can affect data integrity if additional layout guidelines are not followed. few easy points must be considered mainly when routing traces in which switching high currents flow (switching high currents cause voltage spikes across the stray inductance of the traces causing noise that can affect the near traces): when reproducing high current path on internal layers, keep all layers the same size in order to avoid "surrounding" effects that increase noise coupling. keep safe guard distance between high current switching vr traces and data busses, especially if high-speed data busses, to minimize noise coupling. keep safe guard distance or f ilter properly when routing bias traces for i/o sub-systems that must walk near the vr. possible causes of noise can be located in the phase c onnections, mosfets gate drive and input voltage path (from input bulk capa citors and hs drain). also gnd connection must be considered if not insisting on a power ground plane. these connections must be carefully kept far away from noise-sensitive data busses. since the generated noise is mainly due to the switching activity of the vr, noise emissions depend on how fast the current switches. to reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope and thus to increase the switching times: this will cause, as a consequen ce of the higher swit ching time, an increase in switching losses that must be consid ered in the thermal design of the system.
package mechanical data l6727 20/22 10 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com table 6. so-8 mechanical data dim. mm. inch min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 1. d and f does not include mold flash or protrusions . mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004 figure 10. package dimensions
l6727 revision history 21/22 11 revision history table 7. revision history date revision changes 04-dec-2006 1 initial release. 28-feb-2007 2 updated v octh values in table 5 on page 7 06-jun-2007 3 updated figure 1: typical application circuit on page 4 , ta bl e 3 and table 4 on page 6
l6727 22/22 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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